Intel架构下5G第二层网络的最佳实践

Ziyi Li, Leifeng Ruan, Chengqiang Yao, Yao Dong, Na Cui
{"title":"Intel架构下5G第二层网络的最佳实践","authors":"Ziyi Li, Leifeng Ruan, Chengqiang Yao, Yao Dong, Na Cui","doi":"10.1109/GCWkshps45667.2019.9024643","DOIUrl":null,"url":null,"abstract":"This paper investigates a 5G layer 2 network software architecture design on Intel architecture with best practice. We consider to utilize both CPU and hardware acceleration units to implement layer 2 protocols according to 3rd Generation Partnership Project (3GPP). By considering different split options in centralized unit and distributed unit, the proposed software architecture is proved to be able to suit for both scenarios, as well as small cell and macro cell deployment scenarios. Numerical results show that the proposed architecture can be realized on Intel® Xeon® processors with pretty good performance, with high throughput, minimum latency and minimum CPU costs.","PeriodicalId":210825,"journal":{"name":"2019 IEEE Globecom Workshops (GC Wkshps)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A Best Practice of 5G Layer 2 Network on Intel Architecture\",\"authors\":\"Ziyi Li, Leifeng Ruan, Chengqiang Yao, Yao Dong, Na Cui\",\"doi\":\"10.1109/GCWkshps45667.2019.9024643\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper investigates a 5G layer 2 network software architecture design on Intel architecture with best practice. We consider to utilize both CPU and hardware acceleration units to implement layer 2 protocols according to 3rd Generation Partnership Project (3GPP). By considering different split options in centralized unit and distributed unit, the proposed software architecture is proved to be able to suit for both scenarios, as well as small cell and macro cell deployment scenarios. Numerical results show that the proposed architecture can be realized on Intel® Xeon® processors with pretty good performance, with high throughput, minimum latency and minimum CPU costs.\",\"PeriodicalId\":210825,\"journal\":{\"name\":\"2019 IEEE Globecom Workshops (GC Wkshps)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 IEEE Globecom Workshops (GC Wkshps)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/GCWkshps45667.2019.9024643\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE Globecom Workshops (GC Wkshps)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/GCWkshps45667.2019.9024643","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

摘要

本文研究了一种基于Intel架构的5G第二层网络软件架构设计,并给出了最佳实践。根据第三代合作伙伴计划(3GPP),我们考虑同时利用CPU和硬件加速单元来实现第二层协议。通过考虑集中式单元和分布式单元中不同的分离选项,证明了所提出的软件体系结构能够适用于这两种场景,以及小单元和宏单元部署场景。数值结果表明,该架构可以在Intel®Xeon®处理器上实现,具有较高的吞吐量、最小的延迟和最低的CPU成本。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A Best Practice of 5G Layer 2 Network on Intel Architecture
This paper investigates a 5G layer 2 network software architecture design on Intel architecture with best practice. We consider to utilize both CPU and hardware acceleration units to implement layer 2 protocols according to 3rd Generation Partnership Project (3GPP). By considering different split options in centralized unit and distributed unit, the proposed software architecture is proved to be able to suit for both scenarios, as well as small cell and macro cell deployment scenarios. Numerical results show that the proposed architecture can be realized on Intel® Xeon® processors with pretty good performance, with high throughput, minimum latency and minimum CPU costs.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信