Move-to-front and transpose hybrid parallel architectures for high-speed data compression

We give linear systolic array architectures for self organising linear lists using two hybrids schemes of move-to-front and transpose heuristics, attempting to incorporate the best of both methodologies. The arrays provide input every clock cycle and have a number of processors equal to the length of the list n. This design is then implemented to build high-speed lossless data compression hardware for data communication and storage that have high compression ratio for both small and large files.