Scaling up performance of fat nodes for HPC

Future computing systems will integrate an increasing number of compute elements in processors. Such systems must be designed to efficiently scale up and to provide effective synchronization semantics, fast data movement and resource management. At the same time, it is paramount to understand application characteristics to dimension hardware components and interfaces, while adapting the codes to better exploit performance through those features without wasting area or power. This talk will cover multiple technologies targeted to scale up performance of large processors and research insights around synchronization, coherence, bandwidth and resource management, developed during the co-design effort with HPC codes for future systems.