自动集成片上可测试电路

27th ACM/IEEE Design Automation Conference Pub Date : 1990-06-24 DOI:10.1109/DAC.1990.114912

N. Ito

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引用次数: 10

摘要

介绍了一种将可测性电路自动集成到ECL芯片中的系统。包含三种类型的电路:(1)随机访问扫描电路，(2)用于延迟故障测试的时钟抑制电路，(3)用于电路板测试中芯片I/O引脚观察的引脚扫描电路。可测电路中每个门的扇出目的地都被定位在一个芯片上，以保持逻辑网长度在限制范围内。该系统被用于开发新的富士通VP-2000超级计算机。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Automatic incorporation of on-chip testability circuits

A system which automatically incorporates testability circuits into ECL chips is presented. Three types of circuits are incorporated: (1) a random access scan circuit, (2) a clock suppression circuit for delay fault testing, and (3) a pin scan-out circuit for chip I/O pin observation in board testing. Fanout destinations of each gate in the testability circuits are localized on a chip to keep the logical net length within the limit. This system was used to develop the new Fujitsu VP-2000 supercomputer.<>

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来源期刊

27th ACM/IEEE Design Automation Conference

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