{"title":"基于自调节两步积分器的单电流开关阵列无rom DDS","authors":"Haruki Shibue, H. Nosaka","doi":"10.1109/RWS55624.2023.10046322","DOIUrl":null,"url":null,"abstract":"This paper presents a new low-power ROM-less DDS with only a single current-switch array. The phase interpolator reduces the jitter contained in the accumulator overflow signal, so the DDS can obtain pulses with high frequency purity. The newly proposed self-adjusting two-step integrator automatically generates ramp waves of appropriate amplitude, eliminating the need to change the threshold voltage according to the clock frequency. Therefore, the dual current-switch array, which was required in the conventional phase interpolation DDSs, can be reduced by half, which is suitable for low power consumption. The frequency purity of this DDS is tolerant to PVT variations, because the manufacturing variation of the threshold voltage or unit current of the current-switch array is irrelevant to the phase interpolation operation. Experimental results confirm frequency synthesizer operation in which the spurious signal level is reduced to less than that of the accumulator.","PeriodicalId":110742,"journal":{"name":"2023 IEEE Radio and Wireless Symposium (RWS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A ROM-Less DDS with Single Current-Switch Array Using Self-Adjusting Two-Step Integrator\",\"authors\":\"Haruki Shibue, H. Nosaka\",\"doi\":\"10.1109/RWS55624.2023.10046322\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a new low-power ROM-less DDS with only a single current-switch array. The phase interpolator reduces the jitter contained in the accumulator overflow signal, so the DDS can obtain pulses with high frequency purity. The newly proposed self-adjusting two-step integrator automatically generates ramp waves of appropriate amplitude, eliminating the need to change the threshold voltage according to the clock frequency. Therefore, the dual current-switch array, which was required in the conventional phase interpolation DDSs, can be reduced by half, which is suitable for low power consumption. The frequency purity of this DDS is tolerant to PVT variations, because the manufacturing variation of the threshold voltage or unit current of the current-switch array is irrelevant to the phase interpolation operation. Experimental results confirm frequency synthesizer operation in which the spurious signal level is reduced to less than that of the accumulator.\",\"PeriodicalId\":110742,\"journal\":{\"name\":\"2023 IEEE Radio and Wireless Symposium (RWS)\",\"volume\":\"24 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2023-01-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2023 IEEE Radio and Wireless Symposium (RWS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RWS55624.2023.10046322\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 IEEE Radio and Wireless Symposium (RWS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RWS55624.2023.10046322","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A ROM-Less DDS with Single Current-Switch Array Using Self-Adjusting Two-Step Integrator
This paper presents a new low-power ROM-less DDS with only a single current-switch array. The phase interpolator reduces the jitter contained in the accumulator overflow signal, so the DDS can obtain pulses with high frequency purity. The newly proposed self-adjusting two-step integrator automatically generates ramp waves of appropriate amplitude, eliminating the need to change the threshold voltage according to the clock frequency. Therefore, the dual current-switch array, which was required in the conventional phase interpolation DDSs, can be reduced by half, which is suitable for low power consumption. The frequency purity of this DDS is tolerant to PVT variations, because the manufacturing variation of the threshold voltage or unit current of the current-switch array is irrelevant to the phase interpolation operation. Experimental results confirm frequency synthesizer operation in which the spurious signal level is reduced to less than that of the accumulator.