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引用次数: 3
摘要
本文报道了带有n+p+聚顶/底栅极的100nm双栅(DG)满耗尽(FD) SOI NMOS器件的栅极失调效应相关电容行为。二维仿真结果表明，当栅极错位时，器件在VG=0.5V时的栅极-漏极/源极电容(CGD/CGS)的突然下降得到了缓解，这是由于p+底栅极控制的底沟道空穴积累/耗尽减少，边缘电场效应增强。
Gate-Misalignment-Effect Related Capacitance Behavior of a 100nm Double-Gate FD SOI NMOS Device with n+/p+Poly Top/Bottom Gate
This paper reports the gate-misalignment-effect related capacitance behavior of a 100nm double-gate (DG) fully-depleted (FD) SOI NMOS device with the n+p+poly top/bottom gate. Based on the 2D simulation result, with the gate misalignment, the sudden fall in the gate-drain/source capacitance (CGD/CGS) of the device at VG=0.5V is mitigated due to the reduced hole accumulation/ depletion in the bottom channel controlled by the p+bottom gate with the increased fringing electric field effect.
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