{"title":"FM-DCSK通信系统的实验盲定时采集方案","authors":"Xiaochao Li, Xiaofan Lin, Donghui Guo","doi":"10.1109/ICASID.2010.5551521","DOIUrl":null,"url":null,"abstract":"System design and performance are presented for an experimental FM-DCSK radio system with a blind timing acquisition scheme. The transmitter and receiver architecture is proposed, and a novel two-stage blind bit synchronization algorithm for a fast and efficient timing acquisition process is introduced. This synchronization scheme exploits the waveform repetition pattern which naturally present in the DCSK transmitted reference signal structure. The BER performance of such systems is evaluated under AWGN and multi-path channel, the value is fairly close to that of perfect synchronization, which is 0.2dB difference at SNR 10–15dB. Key building blocks of circuit implementation are also presented.","PeriodicalId":391931,"journal":{"name":"2010 International Conference on Anti-Counterfeiting, Security and Identification","volume":"33 1-2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"The experimental blind timing acquisition scheme for FM-DCSK communication system\",\"authors\":\"Xiaochao Li, Xiaofan Lin, Donghui Guo\",\"doi\":\"10.1109/ICASID.2010.5551521\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"System design and performance are presented for an experimental FM-DCSK radio system with a blind timing acquisition scheme. The transmitter and receiver architecture is proposed, and a novel two-stage blind bit synchronization algorithm for a fast and efficient timing acquisition process is introduced. This synchronization scheme exploits the waveform repetition pattern which naturally present in the DCSK transmitted reference signal structure. The BER performance of such systems is evaluated under AWGN and multi-path channel, the value is fairly close to that of perfect synchronization, which is 0.2dB difference at SNR 10–15dB. Key building blocks of circuit implementation are also presented.\",\"PeriodicalId\":391931,\"journal\":{\"name\":\"2010 International Conference on Anti-Counterfeiting, Security and Identification\",\"volume\":\"33 1-2 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-07-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 International Conference on Anti-Counterfeiting, Security and Identification\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICASID.2010.5551521\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 International Conference on Anti-Counterfeiting, Security and Identification","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICASID.2010.5551521","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The experimental blind timing acquisition scheme for FM-DCSK communication system
System design and performance are presented for an experimental FM-DCSK radio system with a blind timing acquisition scheme. The transmitter and receiver architecture is proposed, and a novel two-stage blind bit synchronization algorithm for a fast and efficient timing acquisition process is introduced. This synchronization scheme exploits the waveform repetition pattern which naturally present in the DCSK transmitted reference signal structure. The BER performance of such systems is evaluated under AWGN and multi-path channel, the value is fairly close to that of perfect synchronization, which is 0.2dB difference at SNR 10–15dB. Key building blocks of circuit implementation are also presented.