SRAM可配置fpga中的数据折叠

P. Foulk
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引用次数: 48

摘要

由静态RAM配置的fpga可以快速地从一种逻辑配置转换到另一种逻辑配置。这增加了配置逻辑以实现特定值集的功能的可能性,即将输入折叠到逻辑设计中。本文讨论了基于Algotronix fpga的数据折叠,并给出了一个文本搜索电路作为示例。这种折叠电路比传统电路至少节省了一半的逻辑,如果尽可能地进行数据折叠,则可以节省更多的逻辑。本文还介绍了折叠电路的性能数据,并讨论了其他应用,并提出了数据折叠可行时所需的特性,其中大部分都是Algotronix CAL阵列所具有的。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Data-folding in SRAM configurable FPGAs
FPGAs which are configured by static RAM can be rapidly changed from one logic configuration to another. This raises the possibility of configuring the logic to implement a function for a specific set of values, i.e. folding the inputs into the logic design. The paper discusses data folding with respect to Algotronix FPGAs, presenting a text searching circuit as an example. This folded circuit saves at least half the logic over a conventional circuit, and very much more if data folding is taken as far as possible. It also presents performance figures for the folded circuit, and discusses other applications, and suggests features which are desirable if data folding is to be practicable, most of which are possessed by the Algotronix CAL array.<>
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