{"title":"基于调度算法的快速加工工具吞吐量优化","authors":"Shiladitya Chakravorty, Atirek Wribhu","doi":"10.1109/ASMC.2019.8791797","DOIUrl":null,"url":null,"abstract":"Throughput of certain fast processing tool sets in a semiconductor Fab is sometimes constrained by limitations of FOUP delivery system. The delivery system not being able to keep up with the tools result in a certain throughput loss. This throughput loss can be mitigated by staging the WIP close to tools. However, WIP staging has its limitations. This study presents a methodology to overcome these limitations by staging the WIP just in time for dispatching.","PeriodicalId":287541,"journal":{"name":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"44 2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Throughput Optimization of Fast Processing Tools Using a Dispatching Algorithm\",\"authors\":\"Shiladitya Chakravorty, Atirek Wribhu\",\"doi\":\"10.1109/ASMC.2019.8791797\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Throughput of certain fast processing tool sets in a semiconductor Fab is sometimes constrained by limitations of FOUP delivery system. The delivery system not being able to keep up with the tools result in a certain throughput loss. This throughput loss can be mitigated by staging the WIP close to tools. However, WIP staging has its limitations. This study presents a methodology to overcome these limitations by staging the WIP just in time for dispatching.\",\"PeriodicalId\":287541,\"journal\":{\"name\":\"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)\",\"volume\":\"44 2 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-05-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASMC.2019.8791797\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASMC.2019.8791797","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Throughput Optimization of Fast Processing Tools Using a Dispatching Algorithm
Throughput of certain fast processing tool sets in a semiconductor Fab is sometimes constrained by limitations of FOUP delivery system. The delivery system not being able to keep up with the tools result in a certain throughput loss. This throughput loss can be mitigated by staging the WIP close to tools. However, WIP staging has its limitations. This study presents a methodology to overcome these limitations by staging the WIP just in time for dispatching.
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