带嵌入式滤波的CMOS过采样闭环DAC

2013 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2013-12-23 DOI:10.1109/ASSCC.2013.6691064

Xinying Ding, D. Su, B. Wooley

{"title":"带嵌入式滤波的CMOS过采样闭环DAC","authors":"Xinying Ding, D. Su, B. Wooley","doi":"10.1109/ASSCC.2013.6691064","DOIUrl":null,"url":null,"abstract":"A closed-loop oversampled DAC with embedded reconstruction filtering has been integrated in 0.18-μm CMOS. The architecture provides multi-bit conversion without DEM and 3rd-order filtering of out-of-band noise. At a sampling rate of 10MHz with an OSR of 16, the DAC achieves 61-dB SNDR, 63-dB DR, and 50-dB out-of-band noise suppression, while dissipating 22mW from a 1.2-V supply.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A CMOS oversampled closed-loop DAC with embedded filtering\",\"authors\":\"Xinying Ding, D. Su, B. Wooley\",\"doi\":\"10.1109/ASSCC.2013.6691064\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A closed-loop oversampled DAC with embedded reconstruction filtering has been integrated in 0.18-μm CMOS. The architecture provides multi-bit conversion without DEM and 3rd-order filtering of out-of-band noise. At a sampling rate of 10MHz with an OSR of 16, the DAC achieves 61-dB SNDR, 63-dB DR, and 50-dB out-of-band noise suppression, while dissipating 22mW from a 1.2-V supply.\",\"PeriodicalId\":296544,\"journal\":{\"name\":\"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)\",\"volume\":\"29 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-12-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASSCC.2013.6691064\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2013.6691064","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 2

摘要

在0.18 μm CMOS上集成了一个带重构滤波的闭环过采样DAC。该结构提供无DEM的多位转换和带外噪声的三阶滤波。在采样率为10MHz, OSR为16的情况下，DAC可实现61-dB SNDR、63-dB DR和50-dB带外噪声抑制，同时从1.2 v电源消耗22mW。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

A CMOS oversampled closed-loop DAC with embedded filtering

A closed-loop oversampled DAC with embedded reconstruction filtering has been integrated in 0.18-μm CMOS. The architecture provides multi-bit conversion without DEM and 3rd-order filtering of out-of-band noise. At a sampling rate of 10MHz with an OSR of 16, the DAC achieves 61-dB SNDR, 63-dB DR, and 50-dB out-of-band noise suppression, while dissipating 22mW from a 1.2-V supply.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)

自引率

0.00%

发文量