A. Matrosova, S. Ostanin, I. Kirienko, Virendra Singh
{"title":"部分可编程电路设计","authors":"A. Matrosova, S. Ostanin, I. Kirienko, Virendra Singh","doi":"10.1109/EWDTS.2014.7027067","DOIUrl":null,"url":null,"abstract":"The new approach to partially programmable circuit design that allows masking arbitrary gate faults of a logical circuit is considered. It is supposed that only one gate may be fault. There are reserved blocks CLBs (configurable logic block) based on LUTs (Look up table) that may mask the gate fault. The suggested approach in comparison with the currently in use ones allows masking any gate fault but not the certain stuck-at faults at the gate poles.","PeriodicalId":272780,"journal":{"name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS 2014)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Partially programmable circuit design\",\"authors\":\"A. Matrosova, S. Ostanin, I. Kirienko, Virendra Singh\",\"doi\":\"10.1109/EWDTS.2014.7027067\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The new approach to partially programmable circuit design that allows masking arbitrary gate faults of a logical circuit is considered. It is supposed that only one gate may be fault. There are reserved blocks CLBs (configurable logic block) based on LUTs (Look up table) that may mask the gate fault. The suggested approach in comparison with the currently in use ones allows masking any gate fault but not the certain stuck-at faults at the gate poles.\",\"PeriodicalId\":272780,\"journal\":{\"name\":\"Proceedings of IEEE East-West Design & Test Symposium (EWDTS 2014)\",\"volume\":\"24 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of IEEE East-West Design & Test Symposium (EWDTS 2014)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EWDTS.2014.7027067\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS 2014)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EWDTS.2014.7027067","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The new approach to partially programmable circuit design that allows masking arbitrary gate faults of a logical circuit is considered. It is supposed that only one gate may be fault. There are reserved blocks CLBs (configurable logic block) based on LUTs (Look up table) that may mask the gate fault. The suggested approach in comparison with the currently in use ones allows masking any gate fault but not the certain stuck-at faults at the gate poles.
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