基于Xilinx Kintex7 FPGA和EdkDSP浮点加速器的视频链演示

2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS) Pub Date : 2015-07-19 DOI:10.1109/SAMOS.2015.7363690

J. Kadlec

{"title":"基于Xilinx Kintex7 FPGA和EdkDSP浮点加速器的视频链演示","authors":"J. Kadlec","doi":"10.1109/SAMOS.2015.7363690","DOIUrl":null,"url":null,"abstract":"This paper briefly describes basic Kintex7 FPGA video pipe infrastructure for UTIA demonstrator in the ARTEMIS JU project ALMARVI. The video pipeline is combined with the run-time reprogrammable vector floating point EdkDSP accelerators on the same FPGA chip.","PeriodicalId":346802,"journal":{"name":"2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Video chain demonstrator on Xilinx Kintex7 FPGA with EdkDSP floating point accelerators\",\"authors\":\"J. Kadlec\",\"doi\":\"10.1109/SAMOS.2015.7363690\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper briefly describes basic Kintex7 FPGA video pipe infrastructure for UTIA demonstrator in the ARTEMIS JU project ALMARVI. The video pipeline is combined with the run-time reprogrammable vector floating point EdkDSP accelerators on the same FPGA chip.\",\"PeriodicalId\":346802,\"journal\":{\"name\":\"2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-07-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SAMOS.2015.7363690\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SAMOS.2015.7363690","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 1

摘要

本文简要介绍了ARTEMIS JU项目ALMARVI中用于uta演示器的基本Kintex7 FPGA视频管道基础结构。视频管道与运行时可编程的矢量浮点EdkDSP加速器结合在同一个FPGA芯片上。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Video chain demonstrator on Xilinx Kintex7 FPGA with EdkDSP floating point accelerators

This paper briefly describes basic Kintex7 FPGA video pipe infrastructure for UTIA demonstrator in the ARTEMIS JU project ALMARVI. The video pipeline is combined with the run-time reprogrammable vector floating point EdkDSP accelerators on the same FPGA chip.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)

自引率

0.00%

发文量