CMOS锁存滞后发射极电阻的光电识别

Ming-Jer Chen, J. Jeng, P. Tseng, N. Tsai, Ching-Yuan Wu
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引用次数: 4

摘要

本文提出了一种应用于特殊设计的p-n-p-n结构的光电探测技术,以便准确地确定CMOS闭锁路径中控制I-V特性滞后的基本参数。实验和理论都表明,发射极电阻对磁滞的产生起着重要的作用。作者还描述了三维效应的针组合的迟滞的形成
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Photoemission identification of emitter resistance for CMOS latch-up hysteresis
The authors present a photoemission detection technique applied to a specially designed p-n-p-n structure in order to accurately determine the essential parameters dominating the hysteresis of I-V characteristics in CMOS latchup paths. It is shown experimentally and theoretically that the emitter resistance plays a significant role in producing hysteresis. The authors also describe the three-dimensional effect in terms of pin combinations for the formation of the hysteresis.<>
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