采用柔性时间解耦的并行系统仿真ESL设计

2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS) Pub Date : 2015-07-19 DOI:10.1109/SAMOS.2015.7363702

Jan Weinstock, R. Leupers, G. Ascheid

{"title":"采用柔性时间解耦的并行系统仿真ESL设计","authors":"Jan Weinstock, R. Leupers, G. Ascheid","doi":"10.1109/SAMOS.2015.7363702","DOIUrl":null,"url":null,"abstract":"Engineers of next generation embedded systems heavily rely on virtual platforms as central tools in their design process. Yet, the ever increasing HW/SW complexity degrades the simulation performance of those platforms and threatens their viability as design tools. With multi-core workstations today being widely available, the transition towards parallel simulation technologies seems obvious. Recently published parallel SystemC simulators use time-decoupling to achieve high simulation performance on modern SMP machines. However, those simulators have to identify all cross-thread communication ahead of time. This work presents an approach how to overcome this limitation and to enable time-decoupled simulation for mainstream SystemC simulators, achieving a speedup of up to 3.4× on a quad-core host.","PeriodicalId":346802,"journal":{"name":"2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Parallel SystemC simulation for ESL design using flexible time decoupling\",\"authors\":\"Jan Weinstock, R. Leupers, G. Ascheid\",\"doi\":\"10.1109/SAMOS.2015.7363702\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Engineers of next generation embedded systems heavily rely on virtual platforms as central tools in their design process. Yet, the ever increasing HW/SW complexity degrades the simulation performance of those platforms and threatens their viability as design tools. With multi-core workstations today being widely available, the transition towards parallel simulation technologies seems obvious. Recently published parallel SystemC simulators use time-decoupling to achieve high simulation performance on modern SMP machines. However, those simulators have to identify all cross-thread communication ahead of time. This work presents an approach how to overcome this limitation and to enable time-decoupled simulation for mainstream SystemC simulators, achieving a speedup of up to 3.4× on a quad-core host.\",\"PeriodicalId\":346802,\"journal\":{\"name\":\"2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)\",\"volume\":\"30 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-07-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SAMOS.2015.7363702\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SAMOS.2015.7363702","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 4

摘要

下一代嵌入式系统的工程师在设计过程中严重依赖虚拟平台作为核心工具。然而，不断增加的硬件/软件复杂性降低了这些平台的模拟性能，并威胁到它们作为设计工具的可行性。随着多核工作站的广泛使用，向并行仿真技术的过渡似乎是显而易见的。最近发布的并行SystemC模拟器使用时间解耦来实现现代SMP机器的高仿真性能。然而，这些模拟器必须提前识别所有跨线程通信。这项工作提出了一种克服这一限制的方法，并为主流SystemC模拟器实现了时间解耦仿真，在四核主机上实现了高达3.4倍的加速。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Parallel SystemC simulation for ESL design using flexible time decoupling

Engineers of next generation embedded systems heavily rely on virtual platforms as central tools in their design process. Yet, the ever increasing HW/SW complexity degrades the simulation performance of those platforms and threatens their viability as design tools. With multi-core workstations today being widely available, the transition towards parallel simulation technologies seems obvious. Recently published parallel SystemC simulators use time-decoupling to achieve high simulation performance on modern SMP machines. However, those simulators have to identify all cross-thread communication ahead of time. This work presents an approach how to overcome this limitation and to enable time-decoupled simulation for mainstream SystemC simulators, achieving a speedup of up to 3.4× on a quad-core host.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)

自引率

0.00%

发文量