一种基于reram的单nvm非易失性触发器,采用物联网时代非易失性处理器的自写终止方案,减少了写时间和写功率,减少了写时间分布

Chieh-Pu Lo, Wei-Hao Chen, Zhibo Wang, Albert Lee, Kuo-Hsiang Hsu, Fang Su, Y. King, C. Lin, Yongpan Liu, Huazhong Yang, P. Khalili, Kang L. Wang, Meng-Fan Chang
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引用次数: 19

摘要

最新的非易失性触发器(nvff)支持在触发器(ff)和非易失性存储器(NVM)设备之间本地并行移动数据,从而加快系统的开关操作。以往基于双nvvm的nvff的nvm写次数分布广、周期长,导致nvm写操作的存储能量过大,覆盖导致可靠性下降。这项工作提出了一个使用单个NVM (1R)和自写终止(SWT)的nvFF,能够将ES减少27+x并避免覆盖操作。在制造的65nm ReRAM nvProcessor测试芯片中,所提出的SWT1R nvff实现了关闭/打开操作,Es减少了99%,SWT延迟(TSWT)减少了2.7ns。首次提出了单NVM器件的nvFF。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A ReRAM-based single-NVM nonvolatile flip-flop with reduced stress-time and write-power against wide distribution in write-time by using self-write-termination scheme for nonvolatile processors in IoT era
Recent nonvolatile flip-flops (nvFFs) enable the parallel movement of data locally between flip-flops (FFs) and nonvolatile memory (NVM) devices for faster system power off/on operations. The wide distribution and long period in NVM-write times of previous two-NVM-based nvFFs result in excessive store energy (Es) and over-write induced reliability degradation for NVM-write operations. This work proposes an nvFF using a single NVM (1R) with self-write-termination (SWT), capable of reducing ES by 27+x and avoid over-write operations. In fabricated 65nm ReRAM nvProcessor testchips, the proposed SWT1R nvFFs achieved off/on operations with a 99% reduction in Es and 2.7ns SWT latency (TSWT). For the first time, an nvFF with single NVM device is presented.
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