Matrix Inversion Accelerated MCU Circuit for Image Recognition Pertinent Computation

As the most complex computation in the fundamental matrix manipulation, the operation of matrix inversion limits the processing capability in the field of the image recognition and the pertinent application specified circuit. The intensive computation of matrix inversion is mitigated by efficient algorithms such as the Sherman-Morrison formula and accelerated floating-point multiplication and addition, while still suffering from division operations. Here, we present a high-performance floating-point divider circuit, which is capsuled as an instructor in to a general processor Cortex-M3 MCU to efficiently improve the matrix inversion speed in image recognition. The reconstructed MCU circuits are fully implemented on the Xilinx Spartan6 FPGA platform. Compared to the Xilinx floating point IP, the proposed architecture intensively reduces the division operation time by 82%.