{"title":"基于二维表面电位模型的双栅功函数工程掺杂隧道场效应管性能评估","authors":"R. Bose, J. N. Roy","doi":"10.1109/EDKCON.2018.8770436","DOIUrl":null,"url":null,"abstract":"Two dimensional surface potential model of a work function engineered (WFE) doped double gate (DG) Tunnel Field Effect Transistor (TFET) structure is proposed and verified using TCAD Sentaurus device simulation. The overall electric field is estimated using the proposed model based on which device performance is analyzed. The proposed model is completely physics based and analytic and does not include any fitting parameters or iterative calculation. The proposed TFET structure employs gate which is made of two metals having different thicknesses and work functions acting as tunneling gate and control gate. Such configuration creates a n+ pocket enhancing carrier tunneling probability near source/channel junction. A comparative performance analysis is also performed between our proposed device and its normal double Gate (DG) counterpart.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Performance Assessment of a Double Gate Work Function Engineered Doped Tunnel FET Based on 2D Surface Potential Model\",\"authors\":\"R. Bose, J. N. Roy\",\"doi\":\"10.1109/EDKCON.2018.8770436\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Two dimensional surface potential model of a work function engineered (WFE) doped double gate (DG) Tunnel Field Effect Transistor (TFET) structure is proposed and verified using TCAD Sentaurus device simulation. The overall electric field is estimated using the proposed model based on which device performance is analyzed. The proposed model is completely physics based and analytic and does not include any fitting parameters or iterative calculation. The proposed TFET structure employs gate which is made of two metals having different thicknesses and work functions acting as tunneling gate and control gate. Such configuration creates a n+ pocket enhancing carrier tunneling probability near source/channel junction. A comparative performance analysis is also performed between our proposed device and its normal double Gate (DG) counterpart.\",\"PeriodicalId\":344143,\"journal\":{\"name\":\"2018 IEEE Electron Devices Kolkata Conference (EDKCON)\",\"volume\":\"33 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE Electron Devices Kolkata Conference (EDKCON)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDKCON.2018.8770436\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDKCON.2018.8770436","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Performance Assessment of a Double Gate Work Function Engineered Doped Tunnel FET Based on 2D Surface Potential Model
Two dimensional surface potential model of a work function engineered (WFE) doped double gate (DG) Tunnel Field Effect Transistor (TFET) structure is proposed and verified using TCAD Sentaurus device simulation. The overall electric field is estimated using the proposed model based on which device performance is analyzed. The proposed model is completely physics based and analytic and does not include any fitting parameters or iterative calculation. The proposed TFET structure employs gate which is made of two metals having different thicknesses and work functions acting as tunneling gate and control gate. Such configuration creates a n+ pocket enhancing carrier tunneling probability near source/channel junction. A comparative performance analysis is also performed between our proposed device and its normal double Gate (DG) counterpart.
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