测试工艺缺陷对ECL功率延迟性能的影响

Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's Pub Date : 1991-04-15 DOI:10.1109/VTEST.1991.208164

Jiann-Shiun Yuan, J. Liou, David M. Wu

{"title":"测试工艺缺陷对ECL功率延迟性能的影响","authors":"Jiann-Shiun Yuan, J. Liou, David M. Wu","doi":"10.1109/VTEST.1991.208164","DOIUrl":null,"url":null,"abstract":"The impact of process defects on ECL power-delay product has been evaluated. The authors have developed the modeling equations including the process defects in the delay analysis. The delay equation provides the insight into the sensitivity of various process defects in ECL gate delay. The testing model equations are physics based and can be generalized to digital circuits other than ECL logic.<<ETX>>","PeriodicalId":157539,"journal":{"name":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Testing the impact of process defects on ECL power-delay performance\",\"authors\":\"Jiann-Shiun Yuan, J. Liou, David M. Wu\",\"doi\":\"10.1109/VTEST.1991.208164\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The impact of process defects on ECL power-delay product has been evaluated. The authors have developed the modeling equations including the process defects in the delay analysis. The delay equation provides the insight into the sensitivity of various process defects in ECL gate delay. The testing model equations are physics based and can be generalized to digital circuits other than ECL logic.<<ETX>>\",\"PeriodicalId\":157539,\"journal\":{\"name\":\"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's\",\"volume\":\"19 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1991-04-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VTEST.1991.208164\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VTEST.1991.208164","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 1

摘要

分析了工艺缺陷对ECL功率延迟产品的影响。作者建立了包含延迟分析过程缺陷的建模方程。该延迟方程提供了对各种工艺缺陷在ECL门延迟中的敏感性的洞察。测试模型方程是基于物理的，可以推广到除ECL逻辑以外的数字电路中。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Testing the impact of process defects on ECL power-delay performance

The impact of process defects on ECL power-delay product has been evaluated. The authors have developed the modeling equations including the process defects in the delay analysis. The delay equation provides the insight into the sensitivity of various process defects in ECL gate delay. The testing model equations are physics based and can be generalized to digital circuits other than ECL logic.<>

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's

自引率

0.00%

发文量