{"title":"3D互联与封装:即将成为现实还是梦想?","authors":"E. Beyne","doi":"10.1109/ISSCC.2004.1332632","DOIUrl":null,"url":null,"abstract":"Traditional interconnect schemes are basically two-dimensional. It has long been a dream for system designers to be able to combine multiple integrated circuits by connecting them in the third dimension. Three approaches to the 3D interconnect problem are described: system in a package (3D-SiP), system on a chip (3D-SoC) and 3D integrated circuits (3D-IC).","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"70","resultStr":"{\"title\":\"3D interconnection and packaging: impending reality or still a dream?\",\"authors\":\"E. Beyne\",\"doi\":\"10.1109/ISSCC.2004.1332632\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Traditional interconnect schemes are basically two-dimensional. It has long been a dream for system designers to be able to combine multiple integrated circuits by connecting them in the third dimension. Three approaches to the 3D interconnect problem are described: system in a package (3D-SiP), system on a chip (3D-SoC) and 3D integrated circuits (3D-IC).\",\"PeriodicalId\":273317,\"journal\":{\"name\":\"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)\",\"volume\":\"46 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-09-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"70\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.2004.1332632\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2004.1332632","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
3D interconnection and packaging: impending reality or still a dream?
Traditional interconnect schemes are basically two-dimensional. It has long been a dream for system designers to be able to combine multiple integrated circuits by connecting them in the third dimension. Three approaches to the 3D interconnect problem are described: system in a package (3D-SiP), system on a chip (3D-SoC) and 3D integrated circuits (3D-IC).