两全其美:将分裂制造和伪装集成到3D集成电路的安全驱动CAD流程中

Satwik Patnaik, M. Ashraf, O. Sinanoglu, J. Knechtel
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引用次数: 11

摘要

随着制造业和供应链的全球化,确保集成电路的安全性和可靠性已成为一个紧迫的挑战。分离制造(SM)和布局伪装(LC)是很有前途的技术,可以保护ic的知识产权(IP)免受制造期间和之后的恶意实体(即不受信任的代工厂和最终用户的逆向工程)的侵害。在本文中,我们力求“两全其美”,即SM和LC。为此,我们将这两种技术扩展到3D集成,这是一种基于多个芯片/模具/层的堆叠和互连的新兴设计和制造范式。首先,我们回顾现有技术及其局限性。我们还提出了一种新颖的、实用的、符合当今设计公司商业模式的知识产权盗版威胁模型。接下来,我们将讨论3D集成如何成为SM和LC结合的天然强匹配。我们提出了一个安全驱动的CAD和制造流程,用于面对面(F2F) 3D ic,以及互连的混淆。基于该CAD流程,我们对DRC-clean布局进行了全面的实验。通过广泛的安全分析(也基于一种新的攻击来恢复混淆的F2F互连),我们认为进入下一个第三维度对于有效和高效的IP保护是非常重要的。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Best of Both Worlds: Integration of Split Manufacturing and Camouflaging into a Security-Driven CAD Flow for 3D ICs
With the globalization of manufacturing and supply chains, ensuring the security and trustworthiness of ICs has become an urgent challenge. Split manufacturing (SM) and layout camouflaging (LC) are promising techniques to protect the intellectual property (IP) of ICs from malicious entities during and after manufacturing (i.e., from untrusted foundries and reverse-engineering by end-users). In this paper, we strive for “the best of both worlds,” that is of SM and LC. To do so, we extend both techniques towards 3D integration, an up-and-coming design and manufacturing paradigm based on stacking and interconnecting of multiple chips/dies/tiers. Initially, we review prior art and their limitations. We also put forward a novel, practical threat model of IP piracy which is in line with the business models of present-day design houses. Next, we discuss how 3D integration is a naturally strong match to combine SM and LC. We propose a security-driven CAD and manufacturing flow for face-to-face (F2F) 3D ICs, along with obfuscation of interconnects. Based on this CAD flow, we conduct comprehensive experiments on DRC-clean layouts. Strengthened by an extensive security analysis (also based on a novel attack to recover obfuscated F2F interconnects), we argue that entering the next, third dimension is eminent for effective and efficient IP protection.
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