Planar technology integration of monocrystalline Silicon-membranes using nanoholes

An experimental research on a novelty method of creating monocrystalline Silicon-membranes by using nanoholes is shown in this paper. A Silicon-on-insulator (SOI) wafer is used as a substrate, whose buried oxide (BOX) demonstrates the sacrificial layer for creating the cavities and its top-silicon layer is used as the monocrystalline membrane. This new method uses electron-beam lithography to create oblong nanoholes (120nm*2μm). These holes provide the possibility of sealing the cavity via thermal annealing. This creates a cavity with a monocrystalline membrane. The membrane shows the advantage of a full CMOS integration. Furthermore, this is made only by using planar technology processes which are widely spread and an extra bonding process for sealing the membrane is not needed. Different tasks could also be applicable with this membrane (e.g. 3-D integration).