{"title":"一个11 ppm/°c的CMOS电流参考电路，没有外部元件","authors":"Damian Imbrea, N. Cojan","doi":"10.1109/ISSCS.2013.6651190","DOIUrl":null,"url":null,"abstract":"A new CMOS current reference circuit is described. The circuit designed in 65 nm CMOS standard process operates in the temperature range [-40...+130] °C with supply voltage from 2.1 V to 3.0 V. The reference current is 1 μA ± 0.9 nA having a line sensitivity of 0.5 nA/V and 200 dB power supply rejection ratio at low frequencies. No curvature compensation techniques are used. The circuit occupies 0.0091 mm2 silicon area.","PeriodicalId":260263,"journal":{"name":"International Symposium on Signals, Circuits and Systems ISSCS2013","volume":"38 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A 11 ppm/°c CMOS current reference circuit with no external components\",\"authors\":\"Damian Imbrea, N. Cojan\",\"doi\":\"10.1109/ISSCS.2013.6651190\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new CMOS current reference circuit is described. The circuit designed in 65 nm CMOS standard process operates in the temperature range [-40...+130] °C with supply voltage from 2.1 V to 3.0 V. The reference current is 1 μA ± 0.9 nA having a line sensitivity of 0.5 nA/V and 200 dB power supply rejection ratio at low frequencies. No curvature compensation techniques are used. The circuit occupies 0.0091 mm2 silicon area.\",\"PeriodicalId\":260263,\"journal\":{\"name\":\"International Symposium on Signals, Circuits and Systems ISSCS2013\",\"volume\":\"38 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-07-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Symposium on Signals, Circuits and Systems ISSCS2013\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCS.2013.6651190\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Symposium on Signals, Circuits and Systems ISSCS2013","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCS.2013.6651190","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 11 ppm/°c CMOS current reference circuit with no external components
A new CMOS current reference circuit is described. The circuit designed in 65 nm CMOS standard process operates in the temperature range [-40...+130] °C with supply voltage from 2.1 V to 3.0 V. The reference current is 1 μA ± 0.9 nA having a line sensitivity of 0.5 nA/V and 200 dB power supply rejection ratio at low frequencies. No curvature compensation techniques are used. The circuit occupies 0.0091 mm2 silicon area.
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