Internal chip ESD phenomena beyond the protection circuit

V/sub DD/-V/sub SS/ protection design considerations to meet MIL-STD requirements are discussed. Internal chip electrostatic-discharge (ESD) damage due to direct stress applied between V/sub DD/ and V/sub SS/ pins is illustrated, and possible solutions are discussed. It is shown that induced current paths can exist when outputs/inputs are stressed with respect to V/sub DD/ or V/sub SS/ stress, and if the internal layout is not carefully considered, the overall protection level can degrade. An unusual internal ESD phenomenon that was observed for I/O pins stressed with respect to V/sub DD/ is reported. The results show that there exists a window of threshold voltages where the I/O protection is not effective due to interaction with the internal chip layout.<>