T. Haniotakis, E. Kalligeros, D. Nikolos, G. Sidiropulos, Y. Tsiatouhas, H. T. Vergos
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A class of easily path delay fault testable circuits
The number of physical paths in a carry save or modified Booth multiplier, as well as in a non-restoring cellular array divider is prohibitively large for testing all paths for delay faults. Besides, neither all paths are robustly testable nor a basis consisting of SPP-HFRT paths exists. In this paper we present sufficient modifications of the above mentioned circuits so that a basis consisting of SPP-HFRT paths exists. The cardinality of the derived basis is very small. Also, hardware and delay overheads due to the modifications are respectively small and negligible.
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