BDFA多处理器系统中的TMS320C40处理器

The 24th Southeastern Symposium on and The 3rd Annual Symposium on Communications, Signal Processing Expert Systems, and ASIC VLSI Design System Theory Pub Date : 1992-03-01 DOI:10.1109/SSST.1992.712270

K. Ellis

{"title":"BDFA多处理器系统中的TMS320C40处理器","authors":"K. Ellis","doi":"10.1109/SSST.1992.712270","DOIUrl":null,"url":null,"abstract":"A special-purpose processor can he used as a node processor in a processor array for a BDFA multiprocessor system designed to achieve real-time digital signal processing for a specific application. In this paper, I discuss the use of the Texas Instrument TMS320C40 processor as a node processor. My goal is to obtain a system design which can accommodate up to 1000 processors. The design criteria is linear speed-up as additional processors are added until real-time processing is reached for a particular application.","PeriodicalId":359363,"journal":{"name":"The 24th Southeastern Symposium on and The 3rd Annual Symposium on Communications, Signal Processing Expert Systems, and ASIC VLSI Design System Theory","volume":"25 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"TMS320C40 Processor in a BDFA Multiprocessor System\",\"authors\":\"K. Ellis\",\"doi\":\"10.1109/SSST.1992.712270\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A special-purpose processor can he used as a node processor in a processor array for a BDFA multiprocessor system designed to achieve real-time digital signal processing for a specific application. In this paper, I discuss the use of the Texas Instrument TMS320C40 processor as a node processor. My goal is to obtain a system design which can accommodate up to 1000 processors. The design criteria is linear speed-up as additional processors are added until real-time processing is reached for a particular application.\",\"PeriodicalId\":359363,\"journal\":{\"name\":\"The 24th Southeastern Symposium on and The 3rd Annual Symposium on Communications, Signal Processing Expert Systems, and ASIC VLSI Design System Theory\",\"volume\":\"25 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1992-03-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"The 24th Southeastern Symposium on and The 3rd Annual Symposium on Communications, Signal Processing Expert Systems, and ASIC VLSI Design System Theory\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SSST.1992.712270\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"The 24th Southeastern Symposium on and The 3rd Annual Symposium on Communications, Signal Processing Expert Systems, and ASIC VLSI Design System Theory","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SSST.1992.712270","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

专用处理器可作为BDFA多处理器系统处理器阵列中的节点处理器，用于实现特定应用的实时数字信号处理。在本文中，我讨论了使用德州仪器的TMS320C40处理器作为节点处理器。我的目标是获得一个可以容纳多达1000个处理器的系统设计。设计标准是线性加速，因为添加了额外的处理器，直到达到特定应用程序的实时处理。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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TMS320C40 Processor in a BDFA Multiprocessor System

A special-purpose processor can he used as a node processor in a processor array for a BDFA multiprocessor system designed to achieve real-time digital signal processing for a specific application. In this paper, I discuss the use of the Texas Instrument TMS320C40 processor as a node processor. My goal is to obtain a system design which can accommodate up to 1000 processors. The design criteria is linear speed-up as additional processors are added until real-time processing is reached for a particular application.

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The 24th Southeastern Symposium on and The 3rd Annual Symposium on Communications, Signal Processing Expert Systems, and ASIC VLSI Design System Theory

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