Suppression of MOSFET reverse short channel effect by channel doping through gate electrode

The purpose of this paper is to suppress the reverse short channel effect (RSCE) of 0.18 /spl mu/m CMOS, which leads to the increase in standby current in PLL and output buffer circuits. RSCE is due to the transient enhanced diffusion of the channel profile induced by source/drain (S/D) implantation. We propose a new process in which the boron for nMOS threshold voltage (V/sub th/) adjustment is implanted through the gate electrode after S/D activation annealing over the blanket wafer. It enables nMOS transistor to have less than 0.1 V V/sub th/ roll-up without increasing wafer cost. It can also be applied effectively in the case of less than 0.13 /spl mu/m devices, not being limited to the case of 0.18 /spl mu/m CMOS devices.