3D NAND闪存阵列泄漏建模与优化

2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA) Pub Date : 2018-11-01 DOI:10.1109/CICTA.2018.8706083

Yuzi Song, Zhiliang Xia, Wen-yu Hua, F. Liu, Z. Huo

{"title":"3D NAND闪存阵列泄漏建模与优化","authors":"Yuzi Song, Zhiliang Xia, Wen-yu Hua, F. Liu, Z. Huo","doi":"10.1109/CICTA.2018.8706083","DOIUrl":null,"url":null,"abstract":"In this paper, complicated array leakage current of three-dimensional (3D) vertical channel NAND flash memory has been investigated and optimized. Monte Carlo simulation results show the design of channel hole layout, process variation of channel hole critical dimension are identified to the leakage issue. Experiment results show that the optimized layout, the elliptical outer hole profile and more uniform channel hole critical dimension lead to a significant leakage improvement.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"613 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Modeling and optimization of Array Leakage in 3D NAND Flash Memory\",\"authors\":\"Yuzi Song, Zhiliang Xia, Wen-yu Hua, F. Liu, Z. Huo\",\"doi\":\"10.1109/CICTA.2018.8706083\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, complicated array leakage current of three-dimensional (3D) vertical channel NAND flash memory has been investigated and optimized. Monte Carlo simulation results show the design of channel hole layout, process variation of channel hole critical dimension are identified to the leakage issue. Experiment results show that the optimized layout, the elliptical outer hole profile and more uniform channel hole critical dimension lead to a significant leakage improvement.\",\"PeriodicalId\":186840,\"journal\":{\"name\":\"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)\",\"volume\":\"613 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICTA.2018.8706083\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICTA.2018.8706083","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 2

摘要

本文对三维(3D)垂直通道NAND闪存的复杂阵列漏电流进行了研究和优化。蒙特卡罗仿真结果表明，设计的通道孔布局、工艺变化的通道孔的临界尺寸是确定泄漏问题。实验结果表明，优化后的布置、椭圆的外孔轮廓和更均匀的通道孔临界尺寸显著改善了泄漏量。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Modeling and optimization of Array Leakage in 3D NAND Flash Memory

In this paper, complicated array leakage current of three-dimensional (3D) vertical channel NAND flash memory has been investigated and optimized. Monte Carlo simulation results show the design of channel hole layout, process variation of channel hole critical dimension are identified to the leakage issue. Experiment results show that the optimized layout, the elliptical outer hole profile and more uniform channel hole critical dimension lead to a significant leakage improvement.

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来源期刊

2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)

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