Study of low frequency noise in the 0.18 /spl mu/m silicon CMOS transistors

The low frequency noise in 0.18 /spl mu/m NMOS and PMOS devices is investigated. The devices used throughout this work have been fabricated according to a dual CMOS process with N/sup +/ and P/sup +/ polysilicon metal gate and retrograde well. Prior to the noise analysis, the static characteristics of the devices were measured with an HP 4155 semiconductor parameter analyzer. Subsequently, a theoretical analysis of the drain current noise and the gate voltage noise characteristics is developed in the framework of the carrier number fluctuation model as well as the correlated fluctuation in the mobility model. It is shown experimentally that a close correlation between the drain current spectral density and the transconductance squared dependencies with gate voltage (or drain current) is observed in NMOS devices over a wide current drain. Besides, it is worth mentioning that for the PMOS transistors, there is a significant departure of the noise level from the (g/sub m//I/sub d/)/sup 2/ variation at strong inversion which can be attributed to the correlated mobility fluctuations model. We have developed a simulation based on these flicker noise models and compared the results with experimental noise data. Excellent agreement between the calculations and measurements was observed in the ohmic regime.