流水线FFT处理器

1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461) Pub Date : 1999-10-20 DOI:10.1109/SIPS.1999.822372

Weidong Li, L. Wanhammar

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引用次数: 77

摘要

我们讨论了一种高速、低功耗1024点流水线FFT处理器的设计与实现。主要特点是灵活的内部数据长度和一个新的处理元素。FFT处理器采用标准的0.35 /spl mu/m CMOS工艺，在功耗和芯片面积方面效率很高。

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A pipeline FFT processor

We discuss the design and implementation of a high-speed, low power 1024-point pipeline FFT processor. Key features are flexible internal data length and a novel processing element. The FFT processor, which is implemented in a standard 0.35 /spl mu/m CMOS process, is efficient in terms of power consumption and chip area.

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来源期刊

1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)

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