Manish Arora, Srilatha Manne, Yasuko Eckert, Indrani Paul, N. Jayasena, D. Tullsen
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A comparison of core power gating strategies implemented in modern hardware
Idle power is a significant contributor to overall energy consumption in modern multi-core processors. Cores can enter a full-sleep state, also known as C6, to reduce idle power; however, entering C6 incurs performance and power overheads. Since power gating can result in negative savings, hardware vendors implement various algorithms to manage C6 entry. In this paper, we examine state-of-the-art C6 entry algorithms and present a comparative analysis in the context of consumer and CPU-GPU benchmarks.
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