{"title":"一种用于静电放电保护的新型SCR-LDMOSFET嵌入p区","authors":"J. B. Cheng, S. S. Chen, L. Tian","doi":"10.1109/PEAC.2018.8590616","DOIUrl":null,"url":null,"abstract":"In this paper, a new Silicon Controlled Rectifier and Lateral Double-diffused Metal-Oxide-Semiconductor Field Effect Transistor with shallow P-region (SPSCR- LDMOSFET) is proposed for electrostatic discharge (ESD) protection. The shallow P-region junction causes P-region/N- epi junction being apt to avalanche breakdown. So, trigger voltage is reduced. Furthermore, a new parasitic PNP transistor including the P-region as collector provides another leakage channel for ESD current and then the conductivity modulation in the SCR is weakened. As a result, holding voltage is increased. The physics mechanism of the above high performance is investigated via Technology Computer Aided Design (TCAD) simulation under ESD condition. We also present a detailed analysis of the current paths at trigger point, holding point and second breakdown point.","PeriodicalId":446770,"journal":{"name":"2018 IEEE International Power Electronics and Application Conference and Exposition (PEAC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A New SCR-LDMOSFET Embedded P-Region for Electrostatic Discharge Protection\",\"authors\":\"J. B. Cheng, S. S. Chen, L. Tian\",\"doi\":\"10.1109/PEAC.2018.8590616\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, a new Silicon Controlled Rectifier and Lateral Double-diffused Metal-Oxide-Semiconductor Field Effect Transistor with shallow P-region (SPSCR- LDMOSFET) is proposed for electrostatic discharge (ESD) protection. The shallow P-region junction causes P-region/N- epi junction being apt to avalanche breakdown. So, trigger voltage is reduced. Furthermore, a new parasitic PNP transistor including the P-region as collector provides another leakage channel for ESD current and then the conductivity modulation in the SCR is weakened. As a result, holding voltage is increased. The physics mechanism of the above high performance is investigated via Technology Computer Aided Design (TCAD) simulation under ESD condition. We also present a detailed analysis of the current paths at trigger point, holding point and second breakdown point.\",\"PeriodicalId\":446770,\"journal\":{\"name\":\"2018 IEEE International Power Electronics and Application Conference and Exposition (PEAC)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE International Power Electronics and Application Conference and Exposition (PEAC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/PEAC.2018.8590616\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE International Power Electronics and Application Conference and Exposition (PEAC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/PEAC.2018.8590616","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A New SCR-LDMOSFET Embedded P-Region for Electrostatic Discharge Protection
In this paper, a new Silicon Controlled Rectifier and Lateral Double-diffused Metal-Oxide-Semiconductor Field Effect Transistor with shallow P-region (SPSCR- LDMOSFET) is proposed for electrostatic discharge (ESD) protection. The shallow P-region junction causes P-region/N- epi junction being apt to avalanche breakdown. So, trigger voltage is reduced. Furthermore, a new parasitic PNP transistor including the P-region as collector provides another leakage channel for ESD current and then the conductivity modulation in the SCR is weakened. As a result, holding voltage is increased. The physics mechanism of the above high performance is investigated via Technology Computer Aided Design (TCAD) simulation under ESD condition. We also present a detailed analysis of the current paths at trigger point, holding point and second breakdown point.