A distortion reduction technique for bootstrapped-gate MOS Sample-and-Hold circuits using body-effect compensation

A distortion improvement technique for bootstrapped-gate Sample-and-Hold (S/H) circuits, is proposed. The gate overdrive voltage and conductance of the MOS sampling switch are made constant by cancelling the body-effect induced variations in the threshold-voltage. An amplifier is used to provide appropriate gain in the bootstrapped-gate path. The technique allows the minimized second-harmonic distortion (HD2) by adjusting the gain to Ag =1+kγ1, where kγ1 is the sensitivity of threshold voltage to the source voltage. Furthermore, the S/H distortion remains insensitive to the amplifier op-amp characteristics. Chip prototype measurement results of a single-ended S/H amplifier using 0.18 μm CMOS technology show HD2 improvement of 11 dB over conventional bootstrapped-gate S/H.