Virtex FPGA based flash memory controller for chandrayaan - 2 lander mission

After successful mission Chandrayaan - 1 India decide to launch Chandrayaan - 2. The Chandrayaan - 2 is planned to launch with a lunar orbiter, lander and rover. The lander is accomplishing autonomous soft and safe landing at the south polar region of the moon. For safe and soft landing one of the key elements is the Hazard Detection and avoidance (HDA) system which is under progress. HDA processor is process on landmarks which are based on crater topology on lunar surface from previous mission. Other parameters like matching algorithms, real time data and reference images are required for the correct navigation and exact predicted location of lander. So for storage of this reference images and real time data we required high density, space grade flash memory. For this purpose of storage RTIMS (Radiation tolerant intelligent memory stack) flash memory is used. This RTIMS flash memory controller prepared in Virtex FPGA in HDA processor. This paper presents and gives details of basic architecture, Design, comparison, VHDL implementation and test results of RTIMS flash controller.