基于指令的试验台体系结构

Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) Pub Date : 2005-07-20 DOI:10.1109/IWSOC.2005.76

Ho-Seok Choi, Seungbeom Lee, Sin-Chong Park

{"title":"基于指令的试验台体系结构","authors":"Ho-Seok Choi, Seungbeom Lee, Sin-Chong Park","doi":"10.1109/IWSOC.2005.76","DOIUrl":null,"url":null,"abstract":"This paper presents the synthesizable testbench architecture based on the defined instruction for standalone mode verification. The proposed testbench performs fast emulation with low resource and increases flexibility and reusability with variable description of instructions. To prove the performance of our testbench, we verified IEEE 802.11a PHY baseband system and compare with co-sim mode and modified co-sim mode emulation.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"424 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Instruction based testbench architecture\",\"authors\":\"Ho-Seok Choi, Seungbeom Lee, Sin-Chong Park\",\"doi\":\"10.1109/IWSOC.2005.76\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the synthesizable testbench architecture based on the defined instruction for standalone mode verification. The proposed testbench performs fast emulation with low resource and increases flexibility and reusability with variable description of instructions. To prove the performance of our testbench, we verified IEEE 802.11a PHY baseband system and compare with co-sim mode and modified co-sim mode emulation.\",\"PeriodicalId\":328550,\"journal\":{\"name\":\"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)\",\"volume\":\"424 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-07-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IWSOC.2005.76\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IWSOC.2005.76","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 2

摘要

本文提出了一种基于已定义指令的可综合试验台体系结构，用于单机模式验证。该测试平台以低资源实现了快速仿真，并通过对指令的可变描述提高了灵活性和可重用性。为了验证该试验台的性能，我们对IEEE 802.11a PHY基带系统进行了验证，并与co-sim模式和改进的co-sim模式仿真进行了比较。

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Instruction based testbench architecture

This paper presents the synthesizable testbench architecture based on the defined instruction for standalone mode verification. The proposed testbench performs fast emulation with low resource and increases flexibility and reusability with variable description of instructions. To prove the performance of our testbench, we verified IEEE 802.11a PHY baseband system and compare with co-sim mode and modified co-sim mode emulation.

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Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)

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