{"title":"在先进的CMOS技术中,一种测定由于工艺微负载效应而导致的MOSFET栅极长度减少的电学技术","authors":"Chunbo Liu, J. Ma, Jeongmin Choi","doi":"10.1109/ICMTS.2000.844417","DOIUrl":null,"url":null,"abstract":"A test structure was designed to enable an electrical determination of gate length reduction due to micro-loading effects in poly. A transistor with parallel dummy poly's and transistors with isolated poly's were compared. We propose that DIBL effects be used to extract gate length reduction without being affected by any parasitic resistance in source/drain regions. The results agreed well with cross-section SEM analysis, and were confirmed by the measured and simulated speeds of NAND/NOR ring oscillator circuits.","PeriodicalId":447680,"journal":{"name":"ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"An electrical technique for determining MOSFET gate length reduction due to process micro-loading effects in advanced CMOS technology\",\"authors\":\"Chunbo Liu, J. Ma, Jeongmin Choi\",\"doi\":\"10.1109/ICMTS.2000.844417\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A test structure was designed to enable an electrical determination of gate length reduction due to micro-loading effects in poly. A transistor with parallel dummy poly's and transistors with isolated poly's were compared. We propose that DIBL effects be used to extract gate length reduction without being affected by any parasitic resistance in source/drain regions. The results agreed well with cross-section SEM analysis, and were confirmed by the measured and simulated speeds of NAND/NOR ring oscillator circuits.\",\"PeriodicalId\":447680,\"journal\":{\"name\":\"ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095)\",\"volume\":\"31 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-03-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICMTS.2000.844417\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICMTS.2000.844417","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An electrical technique for determining MOSFET gate length reduction due to process micro-loading effects in advanced CMOS technology
A test structure was designed to enable an electrical determination of gate length reduction due to micro-loading effects in poly. A transistor with parallel dummy poly's and transistors with isolated poly's were compared. We propose that DIBL effects be used to extract gate length reduction without being affected by any parasitic resistance in source/drain regions. The results agreed well with cross-section SEM analysis, and were confirmed by the measured and simulated speeds of NAND/NOR ring oscillator circuits.