{"title":"UNUM:构建多核PowerPC微架构的修补匠玩具方法","authors":"Arvind","doi":"10.1109/VLSID.2006.164","DOIUrl":null,"url":null,"abstract":"Summary form only for tutorial. The goal of the UNUM project is to show that it is possible to synthesize many different PowerPC models (both existing and new variants) quickly by using a library of microarchitectural IP blocks. The IP blocks and modules that we are developing include instruction decoder, branch predictor, speculative execution structures, ALUs, LI and L2 cache structures, and cache-coherence engines. This project in addition to providing PowerPC gateware for others to use, will shed light on how IP blocks should be written to be easily modifiable and reusable.","PeriodicalId":382435,"journal":{"name":"VLSI design (Print)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2006-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"UNUM: A Tinker-Toy Approach to Building Multicore PowerPC Microarchitectures\",\"authors\":\"Arvind\",\"doi\":\"10.1109/VLSID.2006.164\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Summary form only for tutorial. The goal of the UNUM project is to show that it is possible to synthesize many different PowerPC models (both existing and new variants) quickly by using a library of microarchitectural IP blocks. The IP blocks and modules that we are developing include instruction decoder, branch predictor, speculative execution structures, ALUs, LI and L2 cache structures, and cache-coherence engines. This project in addition to providing PowerPC gateware for others to use, will shed light on how IP blocks should be written to be easily modifiable and reusable.\",\"PeriodicalId\":382435,\"journal\":{\"name\":\"VLSI design (Print)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-01-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"VLSI design (Print)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSID.2006.164\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"VLSI design (Print)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSID.2006.164","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
UNUM: A Tinker-Toy Approach to Building Multicore PowerPC Microarchitectures
Summary form only for tutorial. The goal of the UNUM project is to show that it is possible to synthesize many different PowerPC models (both existing and new variants) quickly by using a library of microarchitectural IP blocks. The IP blocks and modules that we are developing include instruction decoder, branch predictor, speculative execution structures, ALUs, LI and L2 cache structures, and cache-coherence engines. This project in addition to providing PowerPC gateware for others to use, will shed light on how IP blocks should be written to be easily modifiable and reusable.