High efficiency crest factor reduction for downlink TD-SCDMA system

The downlink signal in Time Division Synchronous CDMA (TD-SCDMA) system typically has high peak to average power ratio (PAR) due to the multi-code nature of the system. In order to accommodate high peaks, power amplifier (PA) has to operate with considerable back-off, which leads to low operating efficiency. By means of various crest factor reduction (CFR) techniques, the PAR of the transmitted signal can be reduced to a level so as to achieve an efficient utilization of PA. Based on the analyses of this paper, an optimized CFR processor is proposed aiming to provide a more efficient PA while keeping the distortion of the downlink signal to a minimum. This solution has been verified with FPGA implementation and is proved to be of high performance in the TD-SCDMA transmission system.