CML电流模式全加法器，用于2.5 v电源

Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94) Pub Date : 1994-05-25 DOI:10.1109/ISMVL.1994.302210

A. Kazeminejad, K. Navi, D. Etiemble

{"title":"CML电流模式全加法器，用于2.5 v电源","authors":"A. Kazeminejad, K. Navi, D. Etiemble","doi":"10.1109/ISMVL.1994.302210","DOIUrl":null,"url":null,"abstract":"We present the basic structure and performance of CML current mode full adders, that are used as carry save adders (CSA) in combinatorial multipliers. A 1.2 /spl mu/m BiCMOS technology is used for simulations but the schematic assumes a 2.5-V power supply. Compared with binary voltage mode CSAs, the multivalued current mode CSAs have chip area and power dissipation advantage, but speed disadvantage. The current mode version is far more sensitive to power supply and temperature shifts.<<ETX>>","PeriodicalId":137138,"journal":{"name":"Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"1994-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":"{\"title\":\"CML current mode full adders for 2.5-V power supply\",\"authors\":\"A. Kazeminejad, K. Navi, D. Etiemble\",\"doi\":\"10.1109/ISMVL.1994.302210\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We present the basic structure and performance of CML current mode full adders, that are used as carry save adders (CSA) in combinatorial multipliers. A 1.2 /spl mu/m BiCMOS technology is used for simulations but the schematic assumes a 2.5-V power supply. Compared with binary voltage mode CSAs, the multivalued current mode CSAs have chip area and power dissipation advantage, but speed disadvantage. The current mode version is far more sensitive to power supply and temperature shifts.<<ETX>>\",\"PeriodicalId\":137138,\"journal\":{\"name\":\"Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-05-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"15\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISMVL.1994.302210\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISMVL.1994.302210","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 15

摘要

介绍了CML电流模式全加法器的基本结构和性能，该加法器在组合乘法器中用作进位保存加法器。模拟使用了1.2 /spl mu/m的BiCMOS技术，但原理图假设电源为2.5 v。与二值电压模式csa相比，多值电流模式csa在芯片面积和功耗方面具有优势，但在速度方面存在劣势。当前模式的版本对电源和温度变化更加敏感。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

CML current mode full adders for 2.5-V power supply

We present the basic structure and performance of CML current mode full adders, that are used as carry save adders (CSA) in combinatorial multipliers. A 1.2 /spl mu/m BiCMOS technology is used for simulations but the schematic assumes a 2.5-V power supply. Compared with binary voltage mode CSAs, the multivalued current mode CSAs have chip area and power dissipation advantage, but speed disadvantage. The current mode version is far more sensitive to power supply and temperature shifts.<>

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)

自引率

0.00%

发文量