基于FPGA的大整数模乘法

Conference Record of the Thirty-Ninth Asilomar Conference onSignals, Systems and Computers, 2005. Pub Date : 1900-01-01 DOI:10.1109/ACSSC.2005.1599986

R. Beguenane, Jean-Luc Beuchat, J. Muller, S. Simard

{"title":"基于FPGA的大整数模乘法","authors":"R. Beguenane, Jean-Luc Beuchat, J. Muller, S. Simard","doi":"10.1109/ACSSC.2005.1599986","DOIUrl":null,"url":null,"abstract":"Public key cryptography often involves modular multiplication of large operands (160 up to 2048 bits). Several researchers have proposed iterative algorithms whose internal data are carry-save numbers. This number system is unfortunately not well suited to today’s Field Programmable Gate Arrays (FPGAs) embedding dedicated carry logic. We propose to perform modular multiplication in a high-radix carry-save number system, where the sum bit of the well-known carry-save representation is replaced by a sum word. Two digits are then added by means of a small Carry-Ripple Adder (CRA). The originality of our approach is to analyze the modulus in order to select the most efficient high-radix carry-save representation.","PeriodicalId":326489,"journal":{"name":"Conference Record of the Thirty-Ninth Asilomar Conference onSignals, Systems and Computers, 2005.","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Modular Multiplication of Large Integers on FPGA\",\"authors\":\"R. Beguenane, Jean-Luc Beuchat, J. Muller, S. Simard\",\"doi\":\"10.1109/ACSSC.2005.1599986\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Public key cryptography often involves modular multiplication of large operands (160 up to 2048 bits). Several researchers have proposed iterative algorithms whose internal data are carry-save numbers. This number system is unfortunately not well suited to today’s Field Programmable Gate Arrays (FPGAs) embedding dedicated carry logic. We propose to perform modular multiplication in a high-radix carry-save number system, where the sum bit of the well-known carry-save representation is replaced by a sum word. Two digits are then added by means of a small Carry-Ripple Adder (CRA). The originality of our approach is to analyze the modulus in order to select the most efficient high-radix carry-save representation.\",\"PeriodicalId\":326489,\"journal\":{\"name\":\"Conference Record of the Thirty-Ninth Asilomar Conference onSignals, Systems and Computers, 2005.\",\"volume\":\"17 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Conference Record of the Thirty-Ninth Asilomar Conference onSignals, Systems and Computers, 2005.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ACSSC.2005.1599986\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Conference Record of the Thirty-Ninth Asilomar Conference onSignals, Systems and Computers, 2005.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ACSSC.2005.1599986","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 5

摘要

公钥加密通常涉及大操作数的模块化乘法(160到2048位)。一些研究人员提出了迭代算法，其内部数据是进位保存数。不幸的是，这个数字系统不太适合今天的现场可编程门阵列(fpga)嵌入专用进位逻辑。我们建议在一个高基数的进位保存数系统中执行模乘法，其中众所周知的进位保存表示的和位被求和字取代。然后通过一个小的携带纹波加法器(CRA)将两个数字相加。该方法的独创性在于分析模量，以选择最有效的高基数免进位表示。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Modular Multiplication of Large Integers on FPGA

Public key cryptography often involves modular multiplication of large operands (160 up to 2048 bits). Several researchers have proposed iterative algorithms whose internal data are carry-save numbers. This number system is unfortunately not well suited to today’s Field Programmable Gate Arrays (FPGAs) embedding dedicated carry logic. We propose to perform modular multiplication in a high-radix carry-save number system, where the sum bit of the well-known carry-save representation is replaced by a sum word. Two digits are then added by means of a small Carry-Ripple Adder (CRA). The originality of our approach is to analyze the modulus in order to select the most efficient high-radix carry-save representation.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Conference Record of the Thirty-Ninth Asilomar Conference onSignals, Systems and Computers, 2005.

自引率

0.00%

发文量