一种新的具有电子/电阻可调性的广义接地阻抗缩放结构

K. Das, Kogara Naveen Kumar, P. Mouli, M. Srivastava
{"title":"一种新的具有电子/电阻可调性的广义接地阻抗缩放结构","authors":"K. Das, Kogara Naveen Kumar, P. Mouli, M. Srivastava","doi":"10.1109/SPIN.2019.8711599","DOIUrl":null,"url":null,"abstract":"In this research article, an active configuration is proposed which acts similar to a impedance multipliar configuration. This configuration is able to increase or decrease the impedance of any grounded passive network. The presented circuit configuration employs two VDCCs and three grounded resistances along with the impedance to be multiplied. The scaling of impedance can be achieved through resistance variation or bias current variation. The use of only grounded passive elements enhance the suitability for on-chip integration. The working of the presented design has been investigated under non-ideal environment. The validation of behavior of the proposed multiplier circuit has been confirmed by designing and simulating an active filter. All the simulations have been performed in PSPICE Environment with $0.18\\ \\mu\\mathrm{m}$ CMOS technology.","PeriodicalId":344030,"journal":{"name":"2019 6th International Conference on Signal Processing and Integrated Networks (SPIN)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A New Generalized Grounded Impedance Scaling Configuration with Electronic/Resistor Tunability\",\"authors\":\"K. Das, Kogara Naveen Kumar, P. Mouli, M. Srivastava\",\"doi\":\"10.1109/SPIN.2019.8711599\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this research article, an active configuration is proposed which acts similar to a impedance multipliar configuration. This configuration is able to increase or decrease the impedance of any grounded passive network. The presented circuit configuration employs two VDCCs and three grounded resistances along with the impedance to be multiplied. The scaling of impedance can be achieved through resistance variation or bias current variation. The use of only grounded passive elements enhance the suitability for on-chip integration. The working of the presented design has been investigated under non-ideal environment. The validation of behavior of the proposed multiplier circuit has been confirmed by designing and simulating an active filter. All the simulations have been performed in PSPICE Environment with $0.18\\\\ \\\\mu\\\\mathrm{m}$ CMOS technology.\",\"PeriodicalId\":344030,\"journal\":{\"name\":\"2019 6th International Conference on Signal Processing and Integrated Networks (SPIN)\",\"volume\":\"28 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-03-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 6th International Conference on Signal Processing and Integrated Networks (SPIN)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SPIN.2019.8711599\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 6th International Conference on Signal Processing and Integrated Networks (SPIN)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SPIN.2019.8711599","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

摘要

在本研究中,提出了一种类似于阻抗倍增结构的有源结构。这种配置能够增加或减少任何接地无源网络的阻抗。所提出的电路配置采用两个vdcs和三个接地电阻以及要乘以的阻抗。阻抗的缩放可以通过电阻变化或偏置电流变化来实现。仅使用接地的无源元件增强了片上集成的适用性。在非理想环境下,研究了该设计的工作原理。通过设计和仿真有源滤波器,验证了所提乘法器电路的性能。所有仿真均在PSPICE环境下使用$0.18\ \mu\ mathm {m}$ CMOS技术进行。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A New Generalized Grounded Impedance Scaling Configuration with Electronic/Resistor Tunability
In this research article, an active configuration is proposed which acts similar to a impedance multipliar configuration. This configuration is able to increase or decrease the impedance of any grounded passive network. The presented circuit configuration employs two VDCCs and three grounded resistances along with the impedance to be multiplied. The scaling of impedance can be achieved through resistance variation or bias current variation. The use of only grounded passive elements enhance the suitability for on-chip integration. The working of the presented design has been investigated under non-ideal environment. The validation of behavior of the proposed multiplier circuit has been confirmed by designing and simulating an active filter. All the simulations have been performed in PSPICE Environment with $0.18\ \mu\mathrm{m}$ CMOS technology.
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