改变电容比和衬底偏置的自级联编码压控振荡器相位噪声优化

M. Haider, K. Zhu, S. Islam, S. Yuan, M. Mahfouz
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引用次数: 1

摘要

本文报道了一种采用相位噪声优化技术的低压低功率自级联码压控振荡器。带有电容反馈网络的自级联结构在不降低电压净空的情况下提供了更好的相位噪声性能。通过对电容比的优化选择,优化了该压控振荡器的相位噪声性能。该振荡器采用0.18µm RF CMOS工艺制造,工作电压为1.0 V,工作频率为1.30 GHz,在1 MHz偏移时相位噪声为- 114.48 dBc/Hz,输出功率为- 22.27 dBm。测量结果表明,最佳衬底偏压可确保相位噪声最小化。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Phase noise optimization of a self-cascode VCO by changing the capacitor ratio and substrate bias
This paper reports a low-voltage low-power self-cascode VCO with a phase noise optimization technique. Self-cascode structure with capacitive feedback network provides better phase noise performance without degrading the voltage headroom. Phase noise performance of the proposed VCO has been optimized by an optimum selection of capacitor ratio. Fabricated in a 0.18-µm RF CMOS process, the oscillator can work with a supply voltage of 1.0 V, with an operating frequency of 1.30 GHz while providing a phase noise of −114.48 dBc/Hz at 1 MHz offset and an output power of −22.27 dBm. Measurement results indicate that an optimum substrate bias ensures the minimization of phase noise.
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