Effects of Vpass and vertical pitch on 3D SONOS NAND Flash memory operations

Analytical simulations are performed to investigate effects of pass gate bias (Vpass) and vertical pitch scaling on a 3D silicon-oxide-nitride-oxide-silicon (SONOS) NAND Flash string. Maximum programmed threshold voltage (VT) degradation and severe cell-to-cell interference were found as the two vertical length parameters-the gate length (LG) and the inter-layer dielectric length (LILD)-are scaled. Detailed quantitative numerical simulations revealed that the increased electric field between the adjacent memory cells is the main cause for those aforementioned results. Finally, minimum scalable cell-to-cell distance was found in terms of cell-to-cell leakage current. These results will give an allowable vertical scaling margin to the 3-D stacked cylindrical memories.