低功耗自定时基数2除法

ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514) Pub Date : 2000-07-26 DOI:10.1109/LPE.2000.155280

Jae-Hee Won, Kiyoung Choi

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引用次数: 1

摘要

提出了一种低功耗的自定时基数2除法方案。通过将非关键数据路径中的双轨动态电路替换为单轨静态电路，降低了功耗，但通过推测余数计算保持了性能。SPICE仿真结果表明，与全双轨版本相比，该设计可实现33.8 ns的56位尾数分割延迟，能耗降低47%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Low power self-timed radix-2 division

A self-timed radix-2 division scheme for low power consumption is proposed. By replacing dual-rail dynamic circuits in non-critical data paths with single-rail static circuits, power dissipation is decreased, yet performance is maintained by speculative remainder computation. SPICE simulation results show that the proposed design can achieve 33.8-ns latency for 56-bit mantissa division and 47% energy reduction compared to a fully dual-rail version.

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ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514)

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