On the Cascade Implementation of Multiple-Output Sparse Logic Functions

Representation of multiple-output logic functions by Multi-Terminal Binary Decision Diagrams (MTBDDs) is studied for the useful class of sparse logic functions specified by the number of true min-terms. This paper derives upper bounds on the MTBDD width, which determine the size of look-up tables (LUTs) needed for hardware realization of these functions in FPGA logic synthesis. The obtained bounds are generalization of similar known bounds for single-output logic functions. Finally a procedure how to find the optimum mapping of MTBDD to a LUT cascade is presented and illustrated on a set of benchmarks.