{"title":"PCI/PCI-x 66/133 MHz总线的信号完整性表征和建模","authors":"M. Sharawi","doi":"10.1109/MWSCAS.2008.4616843","DOIUrl":null,"url":null,"abstract":"Design and characterization of high speed digital buses and interconnects is an essential part in the computer hardware development process. Signal Integrity (SI) testing and verification examines the signal levels, shapes and timing requirements against specifications. In this work, we present a full SI characterization and modelling of a peripheral component interconnect (PCI) bus as well as a PCI-extended (PCI-x) bus running at 66 MHz/133 MHz, respectively. Laboratory measurements show the compliance with specification timing and signal levels.","PeriodicalId":118637,"journal":{"name":"2008 51st Midwest Symposium on Circuits and Systems","volume":"71 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Signal integrity characterization and modelling of a PCI/PCI-x 66/133 MHz bus\",\"authors\":\"M. Sharawi\",\"doi\":\"10.1109/MWSCAS.2008.4616843\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Design and characterization of high speed digital buses and interconnects is an essential part in the computer hardware development process. Signal Integrity (SI) testing and verification examines the signal levels, shapes and timing requirements against specifications. In this work, we present a full SI characterization and modelling of a peripheral component interconnect (PCI) bus as well as a PCI-extended (PCI-x) bus running at 66 MHz/133 MHz, respectively. Laboratory measurements show the compliance with specification timing and signal levels.\",\"PeriodicalId\":118637,\"journal\":{\"name\":\"2008 51st Midwest Symposium on Circuits and Systems\",\"volume\":\"71 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-09-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 51st Midwest Symposium on Circuits and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MWSCAS.2008.4616843\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 51st Midwest Symposium on Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS.2008.4616843","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Signal integrity characterization and modelling of a PCI/PCI-x 66/133 MHz bus
Design and characterization of high speed digital buses and interconnects is an essential part in the computer hardware development process. Signal Integrity (SI) testing and verification examines the signal levels, shapes and timing requirements against specifications. In this work, we present a full SI characterization and modelling of a peripheral component interconnect (PCI) bus as well as a PCI-extended (PCI-x) bus running at 66 MHz/133 MHz, respectively. Laboratory measurements show the compliance with specification timing and signal levels.
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