VLSI parallel and distributed processing algorithms for multidimensional discrete cosine transforms

A VLSI parallel and distributed computation algorithm has been proposed and mapped onto a VLSI architecture for a 1-D discrete cosine transform (DCT) involving the symmetry property. In this 1-D DCT processor architecture, there are (log/sub 2/2N) DCT processor units (PUs) required for computation of a frame of N-point data with a time complexity of O(N). Further, a proposed 2-D DCT processor architecture requires (M(log/sub 2/2N)+N(log/sub 2/2M)) PUs with a time complexity of O(M+N). An optimal architecture for computation of a multidimensional DCT has been proposed. The 3-D DCT processor architecture requires NL log/sub 2/2M+LM log/sub 2/2N+MN log/sub 2/2L PUs with a time complexity of O(M+N+L). All architectures can be controlled by firmware; hence they are more flexible, efficient, and fault-tolerant and therefore very suitable for VLSI implementation.<>