55纳米CMOS技术的AB类运算放大器

2021 28th International Conference on Mixed Design of Integrated Circuits and System Pub Date : 2021-06-24 DOI:10.23919/MIXDES52406.2021.9497543

Paweł Pieńczuk, W. Pleskacz, Mateusz Teodorowski

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引用次数: 0

摘要

介绍了一种采用UMC CMOS 55nm工艺设计的AB类运算放大器。实现了一种带逆变器输出缓冲器的折叠级联码结构。后布局角和蒙特卡罗模拟确保最小带宽等于2 MHz，直流增益等于85 dB。最小67°的相位裕度保证了电路的稳定性。CMRR和PSRR分别至少为85.9 dB和62.5 dB，允许运算放大器在大多数应用中使用。静态电流消耗不超过25 μA。模具尺寸为85 μm × 67 μm。

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Class AB Operational Amplifier in CMOS 55 nm Technology

A class AB operational amplifier, designed in UMC CMOS 55 nm technology, is presented. A folded-cascode architecture with a inverter output buffer was implemented. Post- layout corners and Monte Carlo simulations ensure the minimum bandwidth equal to 2 MHz and DC gain equal to 85 dB. Phase margin with a minimum of 67° ensures the stability of the circuit. CMRR and PSRR of at least 85.9 dB and 62.5 dB, respectively, allow the operational amplifier to be used in the majority of applications. The static current consumption does not exceed 25 μA. The die dimensions are 85 μm x 67 μm.

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2021 28th International Conference on Mixed Design of Integrated Circuits and System

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