{"title":"聚合PMPP(帕累托调制泊松过程)流量源的ATM多路复用器的损失和延迟行为","authors":"K. S. Chandra, Manuj Sharma, D. S. Guru","doi":"10.1109/ICON.2001.962365","DOIUrl":null,"url":null,"abstract":"Average cell loss and cell delay behavior of a simulated 155 Mbit/s ATM multiplexer is studied for aggregated traffic from a number of Pareto-modulated Poisson process (PMPP) sources. PMPP traffic sources are known to generate self-similar traffic with long-range dependence; the dependence of average cell loss ratio and average cell delay parameters on varying buffer sizes is reported. Inappropriateness of large buffers in reducing the cell loss ratio significantly for self-similar, LRD traffic is established. Results shows that if both average CLR and average cell delay are combined together, increasing buffer sizes beyond a limit increases the delay much more significantly than reducing the CLR.","PeriodicalId":178842,"journal":{"name":"Proceedings. Ninth IEEE International Conference on Networks, ICON 2001.","volume":"107 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Loss and delay behavior of an ATM multiplexer for aggregated PMPP (Pareto-modulated Poisson process) traffic sources\",\"authors\":\"K. S. Chandra, Manuj Sharma, D. S. Guru\",\"doi\":\"10.1109/ICON.2001.962365\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Average cell loss and cell delay behavior of a simulated 155 Mbit/s ATM multiplexer is studied for aggregated traffic from a number of Pareto-modulated Poisson process (PMPP) sources. PMPP traffic sources are known to generate self-similar traffic with long-range dependence; the dependence of average cell loss ratio and average cell delay parameters on varying buffer sizes is reported. Inappropriateness of large buffers in reducing the cell loss ratio significantly for self-similar, LRD traffic is established. Results shows that if both average CLR and average cell delay are combined together, increasing buffer sizes beyond a limit increases the delay much more significantly than reducing the CLR.\",\"PeriodicalId\":178842,\"journal\":{\"name\":\"Proceedings. Ninth IEEE International Conference on Networks, ICON 2001.\",\"volume\":\"107 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2001-10-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings. Ninth IEEE International Conference on Networks, ICON 2001.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICON.2001.962365\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. Ninth IEEE International Conference on Networks, ICON 2001.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICON.2001.962365","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Loss and delay behavior of an ATM multiplexer for aggregated PMPP (Pareto-modulated Poisson process) traffic sources
Average cell loss and cell delay behavior of a simulated 155 Mbit/s ATM multiplexer is studied for aggregated traffic from a number of Pareto-modulated Poisson process (PMPP) sources. PMPP traffic sources are known to generate self-similar traffic with long-range dependence; the dependence of average cell loss ratio and average cell delay parameters on varying buffer sizes is reported. Inappropriateness of large buffers in reducing the cell loss ratio significantly for self-similar, LRD traffic is established. Results shows that if both average CLR and average cell delay are combined together, increasing buffer sizes beyond a limit increases the delay much more significantly than reducing the CLR.