{"title":"基于fpga的事务性内存研究","authors":"S. Grinberg, S. Weiss","doi":"10.1109/EEEI.2006.321125","DOIUrl":null,"url":null,"abstract":"The following outlines an effort to speedup the evaluation of a transactional memory system without loosing accuracy. Instead of using the traditional software simulation techniques we build our system within a large FPGA device. The system elements are a mix of commercially available IP cores and our own design. Together with appropriate runtime monitoring this approach yields a powerful substitute to simulation.","PeriodicalId":142814,"journal":{"name":"2006 IEEE 24th Convention of Electrical & Electronics Engineers in Israel","volume":"70 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"13","resultStr":"{\"title\":\"Investigation of Transactional Memory Using FPGAs\",\"authors\":\"S. Grinberg, S. Weiss\",\"doi\":\"10.1109/EEEI.2006.321125\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The following outlines an effort to speedup the evaluation of a transactional memory system without loosing accuracy. Instead of using the traditional software simulation techniques we build our system within a large FPGA device. The system elements are a mix of commercially available IP cores and our own design. Together with appropriate runtime monitoring this approach yields a powerful substitute to simulation.\",\"PeriodicalId\":142814,\"journal\":{\"name\":\"2006 IEEE 24th Convention of Electrical & Electronics Engineers in Israel\",\"volume\":\"70 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"13\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 IEEE 24th Convention of Electrical & Electronics Engineers in Israel\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EEEI.2006.321125\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 IEEE 24th Convention of Electrical & Electronics Engineers in Israel","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EEEI.2006.321125","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The following outlines an effort to speedup the evaluation of a transactional memory system without loosing accuracy. Instead of using the traditional software simulation techniques we build our system within a large FPGA device. The system elements are a mix of commercially available IP cores and our own design. Together with appropriate runtime monitoring this approach yields a powerful substitute to simulation.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
