特高压SiC功率器件的改进蚀刻多步JTE

Cai-Neng Zhou, Yan Wang, Ruifeng Yue, Gang Dai, Jun-tao Li
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引用次数: 1

摘要

提出了一种用于超高压碳化硅(SiC)功率器件的新型边缘终端,即带有4空间调制缓冲沟槽区域的蚀刻三步结终端扩展(3S-4SMBT-JTE)。与传统的3S-JTE相比,3S-4SMBT-JTE器件的边角峰值电场(EF)大大降低,击穿电压(BV)性能优异,且对蚀刻深度的容忍度较宽。基于90 μm厚漂移层的4H-SiC NPN结构的二维器件仿真结果表明,优化后的3S-4SMBT-JTE可获得超过14 kV的BV,且蚀刻深度窗口宽为1.0 μm,比3S-JTE宽67%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Improved etched multistep JTE for UHV SiC power devices
A novel edge termination, referred to as etched 3-step junction termination extension with 4-space-modulated buffer trench regions (3S-4SMBT-JTE), is presented for ultrahigh voltage silicon carbide (SiC) power devices. In comparison with the traditional 3S-JTE, the 3S-4SMBT-JTE shows greatly reduced peak electric field (EF) around the corners and edges of the device, resulting in a superior breakdown voltage (BV) performance with wide tolerance to etching depth. According to 2-D device simulations based on the 4H-SiC NPN structure with a 90 μm thick drift layer, an optimized 3S-4SMBT-JTE shows that over 14 kV BV is achievable with a wide etching depth window of 1.0 μm, 67% wider than that of 3S-JTE.
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